Building the Chiplet Interconnect for AI Infrastructure

  • No Interposers Required

  • Wire abundant interfaces (1K / 0.25 mm**2)

  • Up to 50% reduction in Chiplet Die Area

  • 50x smaller, 10x less energy/bit, 10x lower upfront cost

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Bridgelet Direct Chiplet Input/Output (DCIO)
Features Benefits Features Benefits
Disaggregates system I/O from memory functions Allows chiplet reuse within or across product families Ultra Short Reach (<500µ) Lower power and area; Higher performance
Die scale interconnect (sub-micron) Higher density and performance; Lower power Protocol Agnostic One PHY for multiple protocols
Enables “Beyond the Reticle” constraint Extend SoC designs Die Scale Interconnect (sub-micron) Higher density and performance; Lower power